Test structures are typically allocated little space in a single layer semiconductor design, physical space being at a premium. Consequently, incorporation of a large test structure or a test structure integrally formed with and located near a functional semiconductor circuit into the single layer semiconductor design are economically prohibitive.
Three dimensional semiconductor structures address such needs by providing an integrally formed test structures located in a peripheral testing layer that is formed above or below a functional layer containing a semiconductor circuit. Formation of the peripheral testing layer adds another dimension, i.e., a third dimension or a “z-dimension,” to the two dimensional semiconductor structures within the functional layer. Further, additional functional layers may be formed on the functional layer. Thus, the peripheral testing layer may incorporate large test structures and test structures located near and integrally formed with the functional layers in the semiconductor structure. Thus, three-dimensional test structures enable incorporation of large test structures within the semiconductor structure.
Further, in a typical single layer semiconductor structure, the number of input/output pins is significantly less than the number of circuits, typically be several orders of magnitude, since test structures and related input/output pins cannot occupy a large spacer. Thus, test patterns, i.e., patterns of 0's and 1's employed to test functionality of a semiconductor circuit such as an array structure or a scan chain, are introduced into and scanned across a semiconductor circuit. Scanning of the test patterns across the semiconductor circuit typically requires at least as many clock cycles as the number of gates per scan chain, and takes a significant amount of test time. A three-dimensional test structure may reduce the test time since the number of input/output pins as well as the contests of test circuitry of the three-dimensional test structure is much more than what is typically included in single layer semiconductor structures, oftentimes providing almost one-to-one ratio between functional devices in functional layers and test devices within the peripheral testing layer.
The peripheral testing layer is typically formed in close proximity to the semiconductor circuits to be tested. Various test circuits, system verification circuits, and diagnostic circuits may be placed within the peripheral testing layer. The circuits within the peripheral testing layer may be designed with relaxed design ground rules, i.e., design ground rules employing dimensions greater than lithographic critical dimensions, to insure that the yield of the three-dimensional semiconductor structure is not limited by the yield of the peripheral layer.
FIGS. 1A-1U show sequential vertical cross-sectional views of an exemplary prior art three-dimensional semiconductor structure during manufacturing and testing. Referring to FIG. 1A, the exemplary prior art three-dimensional semiconductor structure comprises a peripheral test structure substrate (PTSS) 10′ in which a plurality of peripheral test structure substrate (PTSS) via holes 13′ are formed, for example, by lithographic patterning and etching. The PTSS 10′ may comprise a semiconductor or an insulator.
Referring to FIG. 1B, the plurality of PTSS via holes 13′ are filled with a conductive material, such as a metal, and planarized to form a plurality of peripheral test structure substrate (PTSS) vias 14′.
Referring to FIG. 1C, a peripheral test structure layer (PTSL) 20′ is formed on the side of the PTSS 10′ that contains the plurality of the PTSS vias 14′. The PTSL 20′ contains various test circuits described above. The upper surface of the PTSL 20′ may, or may not, contain metal contacts, metal lines, metal vias, or other metal interconnect structures that provide electrical connections to the circuits in the PTSL 20′. The regions of the PTSL 20′ directly above each of the plurality of the PTSS vias 14′ are typically reserved for subsequently making electrical contacts to the plurality of the PTSS vias 14′ as described below.
Referring to FIG. 1D, the PTSL 20′ is patterned to expose top surfaces of the plurality of the PTSS vias 14′. Lithographic methods and an etch may be employed to effect this processing step.
Referring to FIG. 1E, a peripheral test structure interconnect layer (PTSIL) 24′ is formed on the PTSL 20′ and on the exposed surfaces of the plurality of the PTSS vias 14′. The PTSIL 24′ contains metal interconnect structures that provide electrical connection to the various test circuits in the PTSL 20′ and to the plurality of the PTSS vias 14′. Further, the PTSIL 24′ contains peripheral test structure interconnect layer (PTSIL) Controlled Collapse Chip Connection (C4) pads (not shown separately).
Referring to FIG. 1F, C4 balls 30′ are formed on the PTSIL C4 pads within the PTSIL 24′.
Referring to FIG. 1G, the exemplary prior art semiconductor structure containing the PTSS 10′, the plurality of the PTSS vias 14′, the PTSL 20′, the PTSIL 24′, and the C4 balls 30′ is loaded onto a substrate test station (not shown) that is connected to a tester (not shown). A first test probe 80′ to which a first set of test pins 81′ is attached is also loaded into the substrate test station. The first set of test pins 81′ contacts the C4 balls 30′ of the exemplary prior art semiconductor structure, and subsequently, testing is performed to ascertain the functionality of the PTSL 20′ within each semiconductor die. While the yield of the exemplary prior art semiconductor structure is typically high at this point since the PTSL 20′ typically employs relaxed ground rule structures, any defective dies are recorded into a test data tracking system so that the defective dies may be excluded from future testing and eventually discarded.
Referring to FIG. 1H, the exemplary prior art semiconductor structure is unloaded from the substrate test station. A first C4 carrier substrate 90′ containing first carrier C4 pads 92′ is placed over the C4 balls 30′ and C4 bonding is performed as well known in the art. After the C4 bonding, the first C4 carrier substrate 90′ and the PTSS 10′ are structurally connected by the C4 balls 30′ that are bonded to both the PTSIL C4 pads and the first carrier C4 pads 92′.
Referring to FIG. 1I, backside grinding (BSG) processing step is performed to remove a bottom portion of the PTSS 10′ until bottom surfaces of the plurality of the PTSS vias 14′ are exposed. The remaining portion of the PTSS 10′ constitutes a thinned peripheral test structure substrate (TPTSS) 12′.
Referring to FIG. 1J, a first functional layer carrier 41′ having a first functional layer 40′ is brought into contact with the bottom surface of the TPTSS 12′, and aligned to the exposed bottom surfaces of the plurality of the PTSS vias 14′. The first functional layer 40′ comprises a first set of functional semiconductor circuits such as a processor core, various levels of cache memory, embedded memory, or other known semiconductor circuits. Preferably, the first functional layer 40′ contains little or no test circuits since test circuits are primarily formed in the PTSL 20′.
Referring to FIG. 1K, the first functional layer 40′ is bonded to the bottom surface of the TPTSS 12′ by methods known in the art. Thereafter, the first functional layer carrier 41′ is removed. Methods such as separation by a hydrogen implanted layer, or any other method known in the art for separating a carrier substrate may be employed to separate the first functional layer carrier 41′ from the first functional layer 40′.
Referring to FIG. 1L, the first functional layer 40′ is patterned to expose the bottom surfaces of the plurality of the PTSS vias 14′.
Referring to FIG. 1M, a first functional interconnect layer 44′ is formed on the first functional layer 40′ and on the exposed bottom surfaces of the plurality of the PTSS vias 14′. The first functional interconnect layer 44′ contains metal interconnect structures that provide electrical connection to the first set of functional semiconductor circuits in the first functional interconnect layer 40′ and to the plurality of the PTSS vias 14′.
Referring to FIG. 1N, a first 3D assembly carrier 70′ is bonded to the first functional interconnect layer 44′. Bonding methods known in the art may be employed. The first 3D assembly carrier 70′ provides mechanical support to the three-dimensional assembly that it carries.
Referring to FIG. 1O, the first C4 carrier substrate 90′ containing the first carrier C4 pads 92′ are separated from the C4 balls 30′. The bonding between the C4 balls 30′ and the first carrier C4 pads 92′ may be weakened by elevating the temperature of the C4 balls 30′ prior to separation to minimize structural damage to the C4 balls 30′ due to the separation.
The exemplary prior art semiconductor structure containing the TPTSS 12′, the plurality of the PTSS vias 14′, the PTSL 20′, the PTSIL 24′, the C4 balls 30′, the first functional layer 40′, the first functional interconnect layer 44′, and the first 3D assembly carrier 70′ is loaded onto a substrate test station (not shown) that is connected to a tester (not shown). A second test probe 82′ to which a second set of test pins 83′ is attached is also loaded into the substrate test station. The second set of test pins 83′ contacts the C4 balls 30′ of the exemplary prior art semiconductor structure, and subsequently, testing is performed to ascertain the functionality of the first functional layer 40′ within each semiconductor die. Any defective dies are recorded into the test data tracking system so that defective dies may be excluded from future testing and eventually discarded. The second test probe 82′ may, or may not, be the same as the first test probe 80′.
Referring to FIG. 1P, the exemplary prior art semiconductor structure is unloaded from the substrate test station. A second C4 carrier substrate 94′ containing second carrier C4 pads 96′ is placed over the C4 balls 30′ and C4 bonding is performed as well known in the art. After the C4 bonding, the second C4 carrier substrate 94′ and the TPTSS 12′ are structurally connected by the C4 balls 30′ that are bonded to both the PTSIL C4 pads and the second carrier C4 pads 96′.
Referring to FIG. 1Q, the 3D assembly carrier 70′ is separated from the first functional interconnect layer 44′ employing one of the methods of separating a layer from another layer that are known in the art.
Referring to FIG. 1R, a second functional layer carrier 51′ having a second functional layer 50′ is brought into contact with, and aligned to structural features of, the bottom surface of the first functional interconnect layer 44′. The second functional layer 50′ comprises a second set of functional semiconductor circuits, which may contain similar semiconductor components as the first functional layer 40′. Preferably, the second functional layer 50′ contains little or no test circuits since test circuits are primarily formed in the PTSL 20′.
The second functional layer 50′ is bonded to the bottom surface of the first functional interconnect layer 44′ by methods known in the art. Thereafter, the second functional layer carrier 51′ is removed. Methods known in the art for separating a carrier substrate may be employed.
Referring to FIG. 1S, processing steps similar to the processing steps of FIGS. 1L and 1M are performed thereafter to pattern the second functional layer 50′, to expose portions of the first functional interconnect layer 44′, to form a second functional layer 54′ on the second functional layer 50′ and on the exposed portions of the first functional interconnect layer 44′. The second functional interconnect layer 44′ contains metal interconnect structures that provide electrical connection to the second set of functional semiconductor circuits in the second functional interconnect layer 50′ and to the circuit elements in the exposed portions of the first functional interconnect layer 44′.
Referring to FIG. 1T, a second 3D assembly carrier 72′ is bonded to the second functional interconnect layer 54′. Bonding methods known in the art may be employed. The second 3D assembly carrier 72′ provides mechanical support to the three-dimensional assembly that it carries.
Referring to FIG. 1U, the second C4 carrier substrate 94′ containing the second carrier C4 pads 96′ are separated from the C4 balls 30′. The bonding between the C4 balls 30′ and the second carrier C4 pads 96′ may be weakened by elevating the temperature of the C4 balls 30′ prior to separation to minimize structural damage to the C4 balls 30′ due to the separation.
The exemplary prior art semiconductor structure containing the TPTSS 12′, the plurality of the PTSS vias 14′, the PTSL 20′, the PTSIL 24′, the C4 balls 30′, the first functional layer 40′, the first functional interconnect layer 44′, the second functional layer 50′, the second functional interconnect layer 54′, and the second 3D assembly carrier 72′ is loaded onto the substrate test station (not shown) that is connected to a tester (not shown). A third test probe 84′ to which a third set of test pins 85′ is attached is also loaded into the substrate test station. The third set of test pins 85′ contacts the C4 balls 30′ of the exemplary prior art semiconductor structure, and subsequently, testing is performed to ascertain the functionality of the second functional layer 50′ within each semiconductor die. Any defective dies are recorded into the test data tracking system so that defective dies may be excluded from future testing and eventually discarded. The third test probe 84′ may, or may not, be the same as one of the first test probe 80′ and the second test probe 82′.
Processing steps equivalent to FIGS. 1P-1U are repeated performed to build additional functional layers and additional functional interconnect layers on the exemplary prior art semiconductor structure. For attachment of each set of an additional functional layer and an additional functional interconnect layer onto the preexisting portions of the exemplary prior art semiconductor structure and accompanying testing, a set of a functional layer carrier, a 3D assembly carrier, and a C4 carrier substrate are successively bonded and separated. Each of the bonding steps and separation steps involve processing steps that consumes processing time as well as introducing factors that degrade yield of the exemplary prior art semiconductor structure. Further, in the case of the repeated boding and separation of the C4 carrier substrates, the same C4 balls 30′ are employed in each round of the bonding and separation, which tends to degrade yield of the later bonding processes.
In view of the above, there exists a need for simplified and more economical three-dimensional semiconductor structures that are amenable to a high-yield manufacturing sequence.
Specifically, there exists a need for three-dimensional semiconductor structures on which testing of functional layers may be performed without repeated attachment and detachment of 3D assembly carriers and/or C4 carrier substrates, and methods of manufacturing the same.